Position: Senior DV Engineer
Location - San Jose, CA, USA
FTE/FTC
Role Summary
The Senior Engineer DV is responsible for leading and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects.
This role involves technical ownership and close collaboration with design, architecture, and customer teams to achieve verification closure with high quality.
Key Responsibilities Design Verification of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc.
Strong in HVL (UVM / System Verilog / OVM), C/C++, Perl, TCL programming/scripting skills, verification methodologies and flows.
Strong in constraint random verification, assertion writing, coverage analysis, debugging.
Familiarity with ARM cores, formal verification, SV DPI-C is a plus.
Experience with AMS/Low Power verification techniques and verifying mixed signal ICs a plus.
Good knowledge of EDA tools. Experience with signal processing and FPGA based prototyping a plus.
Must be a team player with good oral and written communication skills.
Self-motivated with the ability to work independently and interface effectively with engineers across divisions and remote locations Education BE / BTech / MTech in Electronics, Electrical, or related disciplines.
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